MVP3 cacheable RAM limit query

Discussion relating to Socket 7 hardware.
Post Reply
jeepster
Newbie K6'er
Posts: 10
Joined: Fri Jul 24, 2009 8:54 pm

MVP3 cacheable RAM limit query

Post by jeepster » Fri Feb 11, 2011 9:21 pm

I think the super socket 7 forum is long gone, so I ask here.
On Udo Richter's website, I saw a page for DFI mainboards, which
showed that the maximum cached memory is halved if you have
write back instead of write through. I have not seen this stated before.
Does this apply to all VIA MVP3 boards?
I imagine most enthusiasts are using K6-3 or K6+, so they don't care
about onboard cache anymore.
:?:

moondog
Junior K6'er
Posts: 42
Joined: Sun Dec 12, 2010 5:34 am
Location: Germany
Contact:

Post by moondog » Sat Feb 12, 2011 6:54 am

Hi Jeepster, even though I don´t care about the cacheable area of the mainboard anymore as I´m using a K6-3+ ;) I found out on another forum that this applies on all MVP3 boards as it depends on the chipset itself. Write Back should be a bit faster and uses one Bit as so called "dirty bit" while Write Through doesn´t need this Bit and so it doubles the cacheable area.

There is some longer explanation on this there but I don´t want to translate all of it here ;) Check the link below (it is in german).

http://forum.chip.de/hw-fuer-einsteiger ... -4895.html

Greetings,

Eric

Post Reply