All that you've ever wanted to know about cache, and more

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georgep1
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All that you've ever wanted to know about cache, and more

Post by georgep1 »

This was snagged from the Epox motherboards newsgroup. The poster is Thomas Leibold who was a tremendous source of knowledge on all the Epox MVP3 motherboards. He was responding to a question about cacheable RAM on a motherboard with 512K onboard cache.<br><br>THE ORIGINAL REPLY FROM THOMAS ON CACHEABLE RAM<br><br>The amount of memory cacheable by the Motherboard 512KB cache is always <br>limited to 128MB, no matter what cpu you are using.<br><br>However whether or not you do have any cache on the motherboard or how much<br>of your memory it is able to cache becomes less important if you use a cpu<br>that already has a buildin level 2 cache such as K6-III, K6-2+ or K6-III+.<br>These cpus have an internal level 2 cache that has a very low latency, very<br>high clock speed and is capable of caching the complete address space of the<br>cpu. In many cases you will find that turning of the motherboard cache with<br>one of these cpus does not have any significant effect on your performance<br>(it is application dependent whether or not you still see a benefit from the<br>motherboard cache).<br><br>Thomas<br><br>THE LONG EXPLANATION OF CACHEABLE RAM<br><br>The purpose of any cache is to speed up the access to frequently used data.<br>The main ingredient of a cache is therefore a small amount of memory that<br>is faster (and more expensive) then the memory that it is caching. The first<br>time some data is being read from or written to the memory it is also placed<br>into the cache memory. On subsequent reads the faster cache provides the<br>requested data without the need to wait for the slower memory. This may sound<br>simple, but here is the important part: how do you know whether or not the<br>data you need is inside the cache ? The solution is of course that in addition<br>to the data itself you must also store the address of the memory location to<br>which it belongs. When the next read occurs you compare the address with the<br>one for the data in the cache. If they match you get the data from the cache<br>(Hit) if they don't (Miss) you get the data from memory and place it into the<br>cache. The memory that is used to store the address information for the data<br>in the cache is called tag-ram.<br><br>Using your AMD K6-2+ and the EPoX MVP3C2 as example you have the following<br>cache configuration:<br><br>CPU Core <-> CPU L1 Cache <-> CPU L2 Cache <-> MVP3C2 Cache <-> PC100 SDRAM<br><br>The cpu core (ALU & FPU) gets the data from the cpu internal 64KB L1 cache.<br>This L1 cache is highly specialized and actually divided into two 32KB parts<br>where one is dedicated to the instructions that the cpu executes and the other<br>to the data that is being processed. This L1 cache is very fast (CPU clock<br>speed) and has a very low latency (it only takes very few clock cycles for<br>the cpu to access the L1 cache).<br>Any data needed by the cpu that is not present in the L1 cache is requested<br>from the 128KB L2 cache. This is a general purpose cache (instructions and<br>data) that is also very fast (CPU clock speed) but due to it's larger size<br>requiring some more clock cycles (higher latency) to access it.<br>Both of these cpu internal caches have tag-rams that can keep track of all<br>possible addresses. No matter how much main memory is installed in the system<br>these two fast internal caches can cache it.<br>Any data not present in the two internal caches is requested from the<br>motherboard (VIA MVP3 northbridge to be more precise) through the front-side<br>bus of the cpu chip. This bus operates at only 100MHz which means that any<br>data access through it will be much slower than accesses from the internal<br>caches. The EPoX MVP3C2 has 512KB of SRAM with an access time of 4.5 or 5 ns<br>and 10ns cycle time (10ns cycle time equals a 100MHz clock). It also has a<br>32KB tag-ram with an even slower 8ns access time. Lets look at this cache<br>on the motherboard in some more detail. The SRAM is organized into 65536 (64K)<br>words of 64 bits (8 bytes) each. The burst mode of the SRAM memory chip allows<br>to access the 4 data words in a read or write cycle without any additional<br>delay (just one clock cycle each subsequent word). This is no coincidence<br>because the cache line (the amount of data read or written at once) is 32 bytes<br>or 4 words of 64 bytes. This means that the SRAM contains 16384 cache lines<br>(divide 65536 words by 4 words per cache line).<br>The tag-ram (the one storing the address information for each cache line)<br>is organized into 32768 (32K) words of 8 bits (1 byte) each. Actually half<br>of it is unused since we only have 16384 cachelines for which we need to<br>store the address information. The address information for each cacheline<br>is stored in the 8 databits of the tag-ram. With 8 bits you can only store<br>256 different values and this is exactly the reason why the motherboard cache<br>cannot cache all possible memory addresses. If you multiply 32 bytes per<br>cacheline by 16384 (the number of cachelines in the SRAM) and by 256 (the<br>number of different addresses possible in the tag-ram) you get 128MB. In more<br>general terms the motherboard cache can cache up to 256 times the amount of<br>cache memory (MVP3G2 1MB cache, 256MB cacheable and MVP3G5 2MB cache, 512MB<br>cacheable). A wider tag-ram would allow the motherboard to cache more main<br>memory, but the address comparator in the VIA MVP3 northbridge is limited to<br>8 bits.<br>So what happens if you install more than 128MB of memory ? The cpu L1 and L2<br>cache will cache all memory addresses so there is no problem here. The much<br>slower motherboard cache will only cache memory addresses in the first 128MB.<br>Any access to memory locations above the 128MB mark bypass the motherboard<br>cache, but will still be cached in the cpu L1 and L2 caches.<br><br>The Windows operating system loads most of it's internal functions into the<br>highest memory locations, leaving the lower address areas for applications.<br>If you had a cpu without integrated L2 cache and exceeded the limit of memory<br>cacheable on your motherboard you would experience a significant performance<br>loss. This did indeed happen to a lot of people and this is were the strong<br>recommendations not to exceed the cacheable memory amount come from. With a<br>good cpu that has a fast integrated L2 cache and no cacheable limitation you<br>don't need to worry about that.<br><br>I hope I didn't create more confusion with this lengthy answer. If I did<br>feel free to ask and I'll try to help.<br><br>Thomas<br><br>MORE CLARIFICATION BY THOMAS<br><br>Thanks, but don't try to use it as a technical reference. I left out quite a<br>few things to keep it simple. For example:<br>- the real cacheable limit is only 255 times the size of the cache (one value<br>in the tag-ram is reserved to indicate invalid cachelines).<br>- write-back caching reduces the cacheable memory amount by 50% (one bit in<br>the tag-ram is used to indicate that the cache still contains data that has<br>not yet been written to main memory). This mode is not available on most<br>motherboards because early VIA chips had problems with write-back caching.<br><br><br><br> <p></p><i>Edited by: <A HREF=http://pub70.ezboard.com/ugeorgep1.show ... eorgep1</A> at: 7/4/01 10:12:03 pm<br></i>
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TX97-XE, K6-III+@400, 256 SDRAM, 40 GB WD HD
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thetempleoflove
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Re: All that you've ever wanted to know about cache, and mor

Post by thetempleoflove »

Thanks for posting that. <p></p><i></i>
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blue
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Re: All that you've ever wanted to know about cache, and mor

Post by blue »

yeah thats some good stuff to know <p></p><i></i>
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chevyt98
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All that you've ever wanted to know about cache, and more

Post by chevyt98 »

Georgep1<br>Can you please give me the link to the Epox newsgroup where you came across the Liebold explanation. I remember him from a few years back---- boy does he really know his stuff or another way of putting it is --------boy am I really confussed.<br>Thanks John <p></p><i></i>
georgep1
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Re: All that you've ever wanted to know about cache, and mor

Post by georgep1 »

chevyt98,<br><br>It's on the news.epox.com news server and the news group I found this in epox.english.motherboard. Unfortunately the G2 and G5 news groups went away about a month ago, so any MVP3 advice is now in the general motherboard group. <p></p><i>Edited by: <A HREF=http://pub70.ezboard.com/ugeorgep1.show ... eorgep1</A> at: 7/6/01 6:29:40 pm<br></i>
E-Machines T6000 (AMD64 3200+) (Don't laugh! It absolutely rocks!)
GigaByte K7N400 Pro2, 3200+, 1 GB DDR, 80 GB WD SE
Epox MVPG5, K6-III+@550, 384 SDRAM, 80 GB WD SE
TX97-XE, K6-III+@400, 256 SDRAM, 40 GB WD HD
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