socket 7 cpus @ phase change cooling

Discussion relating to Socket 7 hardware.
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Turrican
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socket 7 cpus @ phase change cooling

Post by Turrican »

Hi guys. :)

i just registered to post my results of overclocking various socket 7 cpus under phase change cooling. :lol:


first cpu:

setup:

amd k6-2+ 550 ACZ 2.0V
epox mvp3g5
2x128mb pc133 cl2 @ 2.0-2-2-5
geforce 4 ti 4600


maximum super pi 1m:

l3 cache was disabled, because above 103mhz fsb nothing is stable.

744mhz (124x6)
Image


max clock 800mhz(133x6). 8)

http://valid.x86-secret.com/show_oc?id=166034



pic:

Image


unfortunately more than 133mhz fsb isn't possible on that board.
although i think the cpu could handle it.

btw. i needed 2.4V for 800mhz ;)

sisoft sandra mem-bandwidth:
Image


everest read:
Image

everest write:
Image

everest latency:
Image


------------------------------------------------------------------------------------------------------


second cpu:

setup:


amd k6-3+ 400 ATZ 1.6V
epox mvp3g5
2x128mb pc133 cl2 @ 2.0-2-2-5
geforce 4 ti 4600



max super pi:

this time with enabled l3-cache ;)
my personal best so far :)

618Mhz (103x6)
Image


max clock 660Mhz(120x5.5) with 2.0V Vcore
http://valid.x86-secret.com/show_oc?id=167075

----------------------------------------------------------------------------------------



third cpu:



setup:


amd k6 266 AFR 2.2V
epox mvp3g5
2x128mb pc133 cl2 @ 2.0-2-2-5
geforce 4 ti 4600



max super pi 1m:

450mhz (100x4.5)
Image


max clock 480mhz (120x4)
http://valid.x86-secret.com/show_oc?id=166278


is this a wr for the k6-2+ ?

unfortunately the k6-3+ won't go higher with 2.0V and with 2.1V it won't even boot. :(

the same for the k6 266. with 2.6V-->no boot.


best regrads :wink:
lazy_kalabok

Post by lazy_kalabok »

lol

yes, its the wr as far as i know! unbelievable ... there is a site where 733 were reached with the 550acr.
many boards have got plls where 150mhz fsb is theoreticaly possible - so the max speed is 900mhz. but noone got them to work until now.
try running the system with the 5,5 multi - you will get higher everest scores.
but i bet you wouldnt beat my M2 @266mhz! :) some results coming next week ...
larrystotler
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Re: socket 7 cpus @ phase change cooling

Post by larrystotler »

Turrican wrote:Hi guys. :)

i just registered to post my results of overclocking various socket 7 cpus under phase change cooling. :lol:

max clock 800mhz(133x6).
I'm guessing it wasn't stable at 800 since you didn't post any benchmarks for it at that speed. Can you run memtest86 on it and report the L1, L2, and mem speepds? It comes with most Linux install cds and also it comes with the Ultimate Boot CD, which is here:

http://www.majorgeeks.com/downloadget.p ... 73a40eda50

Burn the cd, boot it and hit F1 for mainboard tools and F6(unless they changed it again) to start memtest86+.

Could you also post a pic of your motherboard/cooling?

Thanx
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Turrican
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Re: socket 7 cpus @ phase change cooling

Post by Turrican »

larrystotler wrote:
Turrican wrote:Hi guys. :)

i just registered to post my results of overclocking various socket 7 cpus under phase change cooling. :lol:

max clock 800mhz(133x6).
I'm guessing it wasn't stable at 800 since you didn't post any benchmarks for it at that speed. Can you run memtest86 on it and report the L1, L2, and mem speepds? It comes with most Linux install cds and also it comes with the Ultimate Boot CD, which is here:

http://www.majorgeeks.com/downloadget.p ... 73a40eda50

Burn the cd, boot it and hit F1 for mainboard tools and F6(unless they changed it again) to start memtest86+.

Could you also post a pic of your motherboard/cooling?

Thanx

yeah, with 800mhz it wasn't bench stable, but 744mhz was no problem.
i guess it's the high fsb.

ok, i will try "memtest" and will post the results later this week. :D

pics of the setup from my first test with a k6-2 500-->
http://k6plus.com/index.php?name=PNphpB ... f792#14608

if you wish, i'll make more pics and post them later. :wink:
larrystotler
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Re: socket 7 cpus @ phase change cooling

Post by larrystotler »

Turrican wrote:yeah, with 800mhz it wasn't bench stable, but 744mhz was no problem. i guess it's the high fsb.
ok, i will try "memtest" and will post the results later this week. :D
Can you try 5.5x133 for 733Mhz? I've personally found that in a lot of cases the higher FSB speed is more helpful. Still, 740+ Mhz is pretty good. Nice setup. I've never used that type of cooling. I've only done air cooling. For the expense, it's almost always cheaper to buy a faster chip. But, for play, there's nothing like it.
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kalabok
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Post by kalabok »

ok,

as i promised - stunning everest scores.
pc chips m583lmr (aladdin 7)
2x 128 mb pc133
cyrix mII 333gp @ 133x2=266mhz
3d blaster banshee 16mb pci graphic card

everest

read: 594
write: 212
latency: 96,8
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Jim
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Post by Jim »

You are right. That is stunning! "Q" 1) To what do you attribute that score? "Q" 2) How does the machine seem? Does its speed of operation seem to reflect those numbers, or are we dealing w/ another oddity like the rising cache hits generated by running Sandra several times?
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kalabok
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Post by kalabok »

hello jim,

sure, i have to admit that this mII is by far not able to beat the duron it is outperforming in everest. thats more another "effect" like sandra.
here are some benches for different cpus:

all @ 100fsb x 2

pentium mmx (2x8 kb l1) 252/130/187,2

IBM pr233 same as

cyrix 333gp (2x 32 kb l1) 416/151/131,7

amd k6 (2x 32 kb l1) 204/117/186,4

amd k6-2 (2x 32 kb l1) 314/147/237,5

amd k6-2+ same as

amd k6-III+ (2x 32 kb l1 & 128/256kb l2) 312/137/209,3

u see, the cyrix/ibm cpu scores are extraordenary high. i think its because the different way this cpus use their l1 cache - but i do not know nothing.

the cyrix @266 mhz gets realy unstable, i coudnt start sandra to see the bandwidth tests. but the hotcputester gives 638 points, quite good for 266 mhz ... ill try to post the pi 1m later.
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KachiWachi
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Post by KachiWachi »

Remember that a Cyrix has a 64KB unified (4-way) L1 cache, which makes it twice as big as the K6's L1 cache - 32KB data (2-way), 32KB instruction (2-way).

I had an M IIv-433 (100 MHz x 3) in my DFI before I put the K6 in...and it ran quite well at 66MHz x 4 (266 MHz).
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PC #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128 MB EDO. BIOS patched by Jan Steunebrink.
PC #2 - Amptron PM-7900 (M520), i200 non-MMX, 128 MB EDO
PC #3 - HP8766C, PIII-667, 768 MB SDRAM
PC #4 - ASUS P3V4X, PIII-733, 256 MB SDRAM
PC #5 - Gateway 700X, P4-2.0 GHz, 768 MB PC800 RDRAM
PC #6 - COMPAQ Evo N1020v laptop, P4-2.4 GHz, 1 GB PC2700 DDR
PC #7 - Dell Dimension 4600i, P4-2.8 GHz, 512 MB PC2700 DDR
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PC #9 - ??? ;)
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Turrican
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Post by Turrican »

hi guys

sorry, for reporting back to late. in the next few months i'm very busy so i don't have much time for the socket7-system. :(


@ larrystotler

here is the requested memtest run for reporting l1,l2 & mem-speeds

---> with the k6-2+ @ 744mhz :D


Image


is this score good or bad?
i've never used memtest on a socket7-platform so far. ;)


@ kalabok

the everest score is awesome :shock:
Doom5

Post by Doom5 »

I'd be interested to see the IDT Winchip 2, Rise PR433, and a Cyrix MII under phase for kicks...
lazy_kalabok

Post by lazy_kalabok »

to be honest,

i remembered to have had the same effect with my pentium mmx @133mhz fsb. here is my post i did on 13.6.2006 in the sis530 thread:
hello to you guys,

...

i have an interesting remark to add here concerning the k6-2 300 mem latency. after i red your this observation, i decided to try out a pentium mmx on my 133mhz fsb machine (add.: ep-mvp3c2). it booted winxp at 266 mhz, a cpu with 16kb instruction and same data L1 cache. the external cache was turned off.

running everest gave numbers, i can not explain:

read 443 Mb/s
write 103 Mb/s (the only "normal" value)
delay 122,4 ns

running cpumark and hotcpu do give normal values, they are testing the cpu power, not the memory. sandra memory benches - about 280.

it seems to me, that the l2 cache onchip (!!!) is slowing down the memory in a crucial way. even with onboard l2 enabled and 115mhz fsb i get 380 read and 145ns delay ... suggestions?
this effect is even observable on chips, where data and instruction cache are not unified, both 4-way. strange thing about it ...
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