Alladin 5 Users Take note! .pcr data here!!!

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Mr Toastz
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Alladin 5 Users Take note! .pcr data here!!!

Post by Mr Toastz »

I just received this in my email from Rob R: (Thanx Man!)<br>_____________________________________<br><br>I got the .pcr file for the aladdin V chipset finished almost a month ago, but a month ago i also started a new job and had to move, or I would of sent them sooner. Theres still work to be done on them, but the majority of the settings are available. Im only sending the host bridge file at the moment, 10b91541.pcr, cause the others need testing a bit first.<br><br>Rob Ruck<br>_____________________________________<br><br>(cut and paste into notepad, then save as .pcr to make a .pcr file)<br>_____________________________________<br><br><br><br>PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32<br>Copyright (c) 1998 H.Oda!<br><br>[COMMENT]=Author R.Ruck<br>[MODEL]=Aladdin V<br>[VID]=10B9:ALi<br>[DID]=1541:Host Bridge<br><br>(00)=Vendor Identification<br>(01)=Vendor Identification<br>(02)=Device Identification<br>(03)=Device Identification<br><br>(0D)=Device Latency<br><br>[40:6]=Use Internal TAG Ram (1/0 Enables/Disables)<br>[40:5]=Use Internal MESI (0/1 Enables/Disables)<br>[40:4]=M1/M2 Burst & K6 Write Alloc. (1/0 Enables/Disables)<br>[40:3]=M1/M2 Linear Burst (1/0 Enables/Disables)<br>[40:2]=L1 Cache Snoop Point (0-3T 1-2T)<br>[40:1]=L2 Cache Check Point (0-3T 1-2T)<br>[40:0] =L1 Cache (1/0 Enables/Disables)<br><br>[41:6]=Fast DRAM Read (1/0 Enables/Disables)<br>[41:5]=L2 Cache Bank Select (0=1 Bank 1=2 Banks)<br>[41:4]=L2 Cache Type 0=Pipelined Burst SRAM 1=MoSys DRAM Cache<br>[41:3]=L2 Cache Size 00=256k 01=512k 10=1Mb 11=None<br>[41:2]=As Above<br>[41:1]=TAG[9-8] Config 0=Disabled 1=Enabled<br>[41:0] =External TAG Enable (0/1 Enables/Disables)<br><br>[42:7]=L2 TAG Output Delay (1/0 Enables/Disables)<br>[42:6]=Single Read L2 Cache Alloc. (0/1 Enables/Disables)<br>[42:5]=Cache A0000h to BFFFFh (1/0 Enables/Disables)<br>[42:4]=L2 Dirty Bit 0=Normal 1=Force Non-Dirty<br>[42:3]=L2 Force Cache Hit (1/0 Enables/Disables)<br>[42:2]=L2 Cache Miss or Invalidate 0=Normal 1=Force<br>[42:1]=L2 Dirty Bit 0=Normal 1=Force Dirty<br>[42:0] =L2 Cache (1/0 Enables/Disables)<br><br>[43:7]=Force Snoop INV (1/0 Enables/Disables)<br>[43:6]=Dynamic Write Back (1/0 Enables/Disables)<br>[43:5]=DRAM Read Pipe Mode (00-Off 01-Slow 10-Medium 11-Fast)<br>[43:4]=As Above<br>[43:2]=DRAM Single Write Pipe (1/0 Enables/Disables)<br>[43:1]=Fast NAJ (1/0 Enables/Disables)<br>[43:0] =L2 Pipeline Function (1/0 Enables/Disables)<br><br>[44:7]=EDO/FPM DRAM CAS Delay (00-5T 01-4T 10-3T 11-2T)<br>[44:6]=As Above<br>[44:5]=EDO/FPM DRAM Write Timing (00-555 01-444 10-333 11-222)<br>[44:4]=As Above<br>[44:3]=EDO DRAM Read Timing (00-555 01-444 10-333 11-222)<br>[44:2]=As Above<br>[44:1]=FPM DRAM Read Timing (00-666 01-555 10-444 11-333)<br>[44:0] =As Above<br><br>[45:7]=EDO/FPM Cycle Time (00-13T 01-11T 10-10T 11-9T)<br>[45:6]=As Above<br>[45:5]=EDO/FPM RAS Pulse Width (00-7T 01-6T 10-5T 11-4T)<br>[45:4]=As Above<br>[45:3]=EDO/FPM Command Delay (0-3T 1-2T)<br>[45:2]=EDO/FPM CAS Recharge Time (0-2T 1-1T)<br>[45:1]=EDO/FPM RAS Precharge Time (00-6T 01-5T 10-4T 11-3T)<br>[45:0] =As Above<br><br>[46:7]=Fast Back-To-Back (1/0 Enables/Disables)<br>[46:6]=EDO Detect Mode (1/0 Enables/Disables)<br>[46:5]=EDO Det. Timer 00=128- 01=256- 10=512- 11=1024-<br>[46:4]=As Above<br><br>[47:2]=FPM/EDO Bank Miss Insert Wait (1/0 Enables/Disables)<br>[47:1]=EDO/FPM Enhanced Page Mode (1/0 Enables/Disables)<br>[47:0] =FPM/EDO Bank Miss Detection (1/0 Enables/Disables)<br><br>[48:7]=SDRAM Op. Mode 000=Norm 001=NOP 010=PALL<br>[48:6]=(cont.) 011=MRS 100=CBR 111=Auto<br>[48:5]=As Above<br>[48:4]=SDRAM CAS Latency (0-3T 1-2T)<br>[48:3]=SDRAM RAS Precharge (00-5T 01-4T 10-3T 11-2T)<br>[48:2]=As Above<br>[48:1]=SDRAM RAS Cycle Time (00-7T 01-6T 10-5T 11-4T)<br>[48:0] =As Above<br><br>[49:7]=JEDEC "2n Rule" (0/1 Yes/No)<br>[49:6]=SDRAM REFRESH Pre Charge All Banks (1/0 Yes/No)<br>[49:5]=SDRAM Precharge All Insert 1 Wait (1/0 Yes/No)<br>[49:4]=SDRAM Command Insert 1 Wait (1/0 Enables/Disables)<br>[49:3]=SDRAM Enhanced Page Mode (1/0 Enables/Disables)<br>[49:1]=SDRAM Internal Page Detection (1/0 Enables/Disables)<br>[49:0] =SDRAM Pipe Function (1/0 Enables/Disables)<br><br>[4A:7]=Write Buffer Line Threshold (00-2 01-4 10-6 11-8) <br>[4A:6]=As Above<br>[4A:4]=Mixed DRAM Command Interval (0-4T/6T 1-3T/5T)<br>[4A:3]=Supports 2 DIMMs Only (1/0 Enables/Disables)<br>[4A:1]=Fast Next Mode (1/0 Enables/Disables)<br><br>[4B:7]=DRAM Sequencing Parking 0-CPU 1-AGP<br>[4B:6]=AGP HPR Dominate Arbitration (1/0 Enables/Disables)<br>[4B:5]=Arbitration Mode (00-ACPW 01-CAPW 10-CPAW 11-ACPWRR)<br>[4B:4]=As Above<br>[4B:3]=Snoop First (1/0 Enables/Disables)<br>[4B:2]=DRAM Sequencing Bypass Mode (1/0 Enables/Disables)<br>[4B:1]=GART Table Check Point (0-T2 1-T3)<br>[4B:0] =DRAM Posted Write Buffer Rd-Around-Wrt (0/1 Y/N)<br><br>[50:6]=SERRJ Duration Assert 0-1 PCI Clk 1-Till All Errors Cleared<br>[50:5]=SERRJ on Parity/Multi-Bit ECC Error (1/0 Enables/Disables)<br>[50:4]=SERRJ on Single-Bit ECC Error (1/0 Enables/Disables)<br>[50:0] =DRAM Integrity Mode (0-Parity 1-ECC)<br><br>[51:7]=ECC Multi-Bit or Parity First Row Error<br>[51:6]=As Above<br>[51:5]=As Above<br>[51:4]=ECC Multi Bit or Parity Error Flag<br>[51:3]=ECC Single-Bit First Row Error<br>[51:2]=As Above<br>[51:1]=As Above<br>[51:0] =ECC Single-Bit Error Flag<br><br>[53:7]=CPU IDLE SEL TIMER CPU CLKs 00-2 01-4 10-6 11-8<br>[53:6]=As Above<br>[53:5]=Concurrent Posted Write Buffers (0/1 Enables/Disables)<br>[53:4]=Concurrent Posted Write Buffers (0/1 Enables/Disables)<br>[53:3]=DRAM Posted Wrt Buffer Flush Timer 000-4 001-8 010-12<br>[53:2]=(cont.) 110-16 111-32<br>[53:1]=As Above<br>[53:0] =DRAM Posted Wrt Buffer Idle Flush (0/1 Enables/Disables)<br><br>[54:5]=14-15M Mem Location 0=Local 1=Non-Local<br>[54:4]=15-16M Mem Location 0=Local 1=Non-Local<br>[54:3]=Page A-8 As Local Mem 0=Non-Local 1=Local<br>[54:2]=Force 80000h-9FFFFh as Non-Local 0=Local 1=Non-Local<br><br>[55:4]=SMM Page -A/-B Rgn Code/Data Split (1/0 Yes/No)<br>[55:3]=SMRAM Rgn (00=D000 01=A000/B000 10=3000 11=Res.)<br>[55:2]=As Above<br>[55:1]=SMRAM Access Control (1/0 Enables/Disables)<br>[55:0] =Supports SMRAM Mapping (1/0 Enables/Disables)<br><br>[56:7]=DC000h-DFFFFh Shadow Read (1/0 Enables/Disables)<br>[56:6]=D8000h-DBFFFh Shadow Read (1/0 Enables/Disables)<br>[56:5]=D4000h-D7FFFh Shadow Read (1/0 Enables/Disables)<br>[56:4]=D0000h-D3FFFh Shadow Read (1/0 Enables/Disables)<br>[56:3]=CC000h-CFFFFh Shadow Read (1/0 Enables/Disables)<br>[56:2]=C8000h-CBFFFh Shadow Read (1/0 Enables/Disables)<br>[56:1]=C4000h-C7FFFh Shadow Read (1/0 Enables/Disables)<br>[56:0] =C0000h-C3FFFh Shadow Read (1/0 Enables/Disables)<br><br>[57:7]=FC000h-FFFFFh Shadow Read (1/0 Enables/Disables)<br>[57:6]=F8000h-FBFFFh Shadow Read (1/0 Enables/Disables)<br>[57:5]=F4000h-F7FFFh Shadow Read (1/0 Enables/Disables)<br>[57:4]=F0000h-F3FFFh Shadow Read (1/0 Enables/Disables)<br>[57:3]=EC000h-EFFFFh Shadow Read (1/0 Enables/Disables)<br>[57:2]=E8000h-EBFFFh Shadow Read (1/0 Enables/Disables)<br>[57:1]=E4000h-E7FFFh Shadow Read (1/0 Enables/Disables)<br>[57:0] =E0000h-E3FFFh Shadow Read (1/0 Enables/Disables)<br><br>[58:7]=DC000h-DFFFFh Shadow Write (1/0 Enables/Disables)<br>[58:6]=D8000h-DBFFFh Shadow Write (1/0 Enables/Disables)<br>[58:5]=D4000h-D7FFFh Shadow Write (1/0 Enables/Disables)<br>[58:4]=D0000h-D3FFFh Shadow Write (1/0 Enables/Disables)<br>[58:3]=CC000h-CFFFFh Shadow Write (1/0 Enables/Disables)<br>[58:2]=C8000h-CBFFFh Shadow Write (1/0 Enables/Disables)<br>[58:1]=C4000h-C7FFFh Shadow Write (1/0 Enables/Disables)<br>[58:0] =C0000h-C3FFFh Shadow Write (1/0 Enables/Disables)<br><br>[59:7]=FC000h-FFFFFh Shadow Write (1/0 Enables/Disables)<br>[59:6]=F8000h-FBFFFh Shadow Write (1/0 Enables/Disables)<br>[59:5]=F4000h-F7FFFh Shadow Write (1/0 Enables/Disables)<br>[59:4]=F0000h-F3FFFh Shadow Write (1/0 Enables/Disables)<br>[59:3]=EC000h-EFFFFh Shadow Write (1/0 Enables/Disables)<br>[59:2]=E8000h-EBFFFh Shadow Write (1/0 Enables/Disables)<br>[59:1]=E4000h-E7FFFh Shadow Write (1/0 Enables/Disables)<br>[59:0] =E0000h-E3FFFh Shadow Write (1/0 Enables/Disables)<br><br>[5A:7]=DC000h-DFFFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:6]=D8000h-DBFFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:5]=D4000h-D7FFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:4]=D0000h-D3FFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:3]=CC000h-CFFFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:2]=C8000h-CBFFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:1]=C4000h-C7FFFh Shadow Cache (1/0 Enables/Disables)<br>[5A:0] =C0000h-C3FFFh Shadow Cache (1/0 Enables/Disables)<br><br>[5B:7]=FC000h-FFFFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:6]=F8000h-FBFFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:5]=F4000h-F7FFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:4]=F0000h-F3FFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:3]=EC000h-EFFFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:2]=E8000h-EBFFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:1]=E4000h-E7FFFh Shadow Cache (1/0 Enables/Disables)<br>[5B:0] =E0000h-E3FFFh Shadow Cache (1/0 Enables/Disables)<br><br>[5D:4]=Ignore DMWBF When Latency Is Out (1/0 Yes/No)<br>[5D:2]=CLKEN for Notebook Pwr Saving (1/0 Yes/No)<br>[5D:1]=DRAM Gated Clock Timer (00-12 01/10-8 11-4)<br>[5D:0] =As Above<br><br>[5E:7]=FPM/EDO Refresh Mode (0-CAS then RAS 1-RAS Only)<br>[5E:6]=EDO/FPM DRAM Self-Refresh (1/0 Enables/Disables)<br>[5E:5]=Refresh Period (00-/1 01-/2 10-/4 11-/8) <br>[5E:4]=As Above<br>[5E:3]=DRAM Refresh Queing (1/0 Enables/Disables)<br>[5E:2]=DRAM Refresh Period in CPU Clks (000-1024<br>[5E:1]=(cont.) 001-2048 010-4096 011-8192 100-16384)<br>[5E:0] =As Above<br><br>[5F:7]=Enhanced Page Mode Counter (00-4 01-8 10-12 11-16)<br>[5F:6]=As Above<br>[5F:0] =DRAM Refresh Function (1/0 Enables/Disables)<br><br>[70:7]=ROW7 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:6]=ROW6 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:5]=ROW5 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:4]=ROW4 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:3]=ROW3 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:2]=ROW2 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:1]=ROW1 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br>[70:0] =ROW0 sets to 256Mbit SDRAM (1/0 Enables/Disables)<br><br>[71:7]=Number of SDRAM Banks for ROW7 (0-2 1-4)<br>[71:6]=Number of SDRAM Banks for ROW6 (0-2 1-4)<br>[71:5]=Number of SDRAM Banks for ROW5 (0-2 1-4)<br>[71:4]=Number of SDRAM Banks for ROW4 (0-2 1-4)<br>[71:3]=Number of SDRAM Banks for ROW3 (0-2 1-4)<br>[71:2]=Number of SDRAM Banks for ROW2 (0-2 1-4)<br>[71:1]=Number of SDRAM Banks for ROW1 (0-2 1-4)<br>[71:0] =Number of SDRAM Banks for ROW0 (0-2 1-4)<br><br>[72:7]=SDRAM RAS to CAS Delay (0-3 1-2)<br>[72:6]=Enable Seperate SDRAM RAS to CAS Delay (1/0 Yes/No)<br>[72:2]=Delay SDRAM Controller 1 Clk (0/1 Enables/Disables)<br>[72:1]=Delay 1 CPU Clk for 100Mhz (1/0 Enables/Disables)<br>[72:0] =SDRAM 4 Data Duration (1/0 Enables/Disables)<br><br>[73:4]=Clk Delay of DRAM Read Pipe (00-0 01-1 10-2 11-3)<br>[73:3]=As Above<br>[73:2]=DRAM Read Pipe Function (1/0 Enables/Disables)<br>[73:1]=SDRAM Cmd & Data Output Pipeline (1/0 Yes/No)<br>[73:0] =75-100Mhz MD Output Pipe (1/0 Enables/Disables)<br><br>[8D:4]=Miss Read Pending Delay Timeout Retry (0/1 Yes/No)<br>[8D:3]=Internal Write Bus Pipeline Function (1/0 Yes/No)<br>[8D:2]=PCI Freq. Mode (110-2X 101-2.5X 011-3X)<br>[8D:1]=As Above<br>[8D:0] =As Above<br><br>[C8:7]=AGP Read Buffer Depth (0-16 QW 1-32 QW)<br>[C8:4]=AGP Buffer Space Available<br>[C8:0] =AGP Request Queue Depth (0-8 1-16)<br> <p></p><i>Edited by: <A HREF=http://pub70.ezboard.com/umrtoastz.show ... uage=EN>Mr Toastz</A>  <IMG HEIGHT=10 WIDTH=10 SRC=http://www.ezboard.com/ezgfx/gicons/black_ball.gif BORDER=0> at: 8/11/01 6:20:56 pm<br></i>
K6III
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Re: Alladin 5 Users Take note! .pcr data here!!!

Post by K6III »

I'm doing something wrong.<br>I can only save this as a '.txt ' file.<br>In Notepad I'm offered a choice of 'all files' or 'text documents'.<br>Either way it saves it as a '.txt' file.<br>What am I doing wrong?<br><br>Milt<br> <p></p><i></i>
Mr Toastz
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Re: Alladin 5 Users Take note! .pcr data here!!!

Post by Mr Toastz »

OK, here's what I did...<br><br>Find the old windows winfile manager (the file cabinet icon) and open it. Find your Aladdin .pcr file and rename it using the file options. <br><br>Mine was in C<!--EZCODE EMOTICON START :\ --><img src=http://www.ezboard.com/intl/aenglish/im ... ohwell.gif ALT=":\"><!--EZCODE EMOTICON END--> windows <p>My sig<br><embed src="http://k6plus.50megs.com/tjstuff/toastsig2.swf" width=420 height=120></p><i></i>
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Revhead
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Re: Alladin 5 Users Take note! .pcr data here!!!

Post by Revhead »

Okay, excuse my ignorance, but what do I do with this as an Aladdin 5 user?<br> <p>RevheadAMD K6-III+ 450@600Mhz (6x100) 2.0v SP-A586B Rev A; ALI Aladdin V, 512K L3, BIOS A586B Ver:A.9, FOP32 fan, 128RAM, GeForce2MX 200 32M, W98. </p><i></i>
Thanks, Revhead
XP-M Barton 2500+@2530(11.5x220), Albatron KX18D Pro II, Antec 480W, TT Silent Boost 90mm, 2x256 DC Kingmax PC3500, RAID 2x80G SATA, GF2MX400, NEC 3500, LiteOn 832s, Liteon 166s, XP Pro SP1a
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georgep1
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Re: Alladin 5 Users Take note! .pcr data here!!!

Post by georgep1 »

Revhead,<br><br>Your sig here has MX 200, but your sig at amdzone has MX 400. I assume it's an MX 400 since you got 4000 3DMarks at default resolution? <p></p><i></i>
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Revhead
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Re: Alladin 5 Users Take note! .pcr data here!!!

Post by Revhead »

Georgep1,<br>My apologies. Forgot to update my sig since I upgraded to the MX400.<br> <p>RevheadAMD K6-III+ 450@600Mhz (6x100) 2.0v SP-A586B Rev A; ALI Aladdin V, 512K L3, BIOS A586B Ver:A.9, FOP32 fan, 128RAM, GeForce2MX 200 32M, W98. </p><i></i>
Thanks, Revhead
XP-M Barton 2500+@2530(11.5x220), Albatron KX18D Pro II, Antec 480W, TT Silent Boost 90mm, 2x256 DC Kingmax PC3500, RAID 2x80G SATA, GF2MX400, NEC 3500, LiteOn 832s, Liteon 166s, XP Pro SP1a
K6-III+450@600(6x100) 2.1v, FOP32, SP-A586B, 512M PC133, 20G 100/7200, Kyro II, Vibra128, XP Pro SP1a (retired)
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Mr Toastz
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Revhead, welcome to the 4000 SS7/3DMark 2000 club, btw!

Post by Mr Toastz »

The above data allows you to see what the various northbridge registers do in the WPCredit program. We have had MVP3 data for a while, but you Aladdin guys have been lacking a good .pcr file for a bit.<br><br>As to which registers to tweak and such, I don't use your chipset so I am not sure what tweaks work well. Relay uses the Ali Chipset, though, and he is experimenting a bit right now I am sure.<br><br>Other Aladdin users are of course free to comment. <p></p><i></i>
bruk2
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Some settings to get you started

Post by bruk2 »

Below are my settings from wpcrset, check what they do in wpcredit, and check if they apply to you:<br><br>49 = ef<br>4a = b0<br>42 = 01<br>5e = 48<br>48 = 1b<br>53 = c1<br>57 = f0<br>58 = 03<br>59 = f0<br>5a = 03<br>5b = f0<br>43 = f7<br>72 = c7 <p></p><i></i>
cake
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Re: Some settings to get you started

Post by cake »

^ bump ^<br><br>Seing there's a lot more people with ALi chipset around these days I think it was time <!--EZCODE EMOTICON START ;) --><img src=http://www.ezboard.com/intl/aenglish/im ... s/wink.gif ALT=";)"><!--EZCODE EMOTICON END--> <br> <p>------------------------------[ my rig ]------------------------------<br>K6-3+ 450@577 (115 x 5), Gigabyte GA-5AX rev5.2<br>386 MB generic RAM<br>15 GB Quantum Fireball LCT + 60 GB Seagate Barracuda IV<br>Radeon 8500LE @ 294/326 MHz (core/mem)<br>SB Live! Value with homemade digital I/O add-on<br>3com 3C905-TX NIC + Netgear FA312 NIC</p><i></i>
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davidbec01

PCR for MVP3

Post by davidbec01 »

Hi all I lost all my files in a recent computer accident. CAn you make the MVP3 pcr file available in the Downloads section please?

Thanks

davidbec01 - previously davidbec but I lost my password as well.
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Wiggy
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Post by Wiggy »

:oops: Don't wanna sound like to much of a dumb ass, but what could this WPCredit do for me.

Performance? Does it get us any closer to the Socket 7 Holy Grale - the 1/4 divider.

A good basic guide would be sweet.

Cheers for yer 'elp.
forciano

Post by forciano »

only testing and alot of reboots and tests will tell you what are the best settings for your system, you can try this page as a guide to what some of the setting do (its lacks some bios setting)
http://www.rojakpot.com/default.aspx?location=1
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